ninja3011 Goto Github PK

100daysofrtl

2048-ai

The iconic 2048 game combined with an AI bot for finishing it in the most efficient mannerr

8bitcomputer

Eklavya project to simulate and build Ben Eaters 8 Bit COmputer

block_based_circuit_design

GSoC 2021, FOSSi Foundation

certificates

chisel-examples

embedded_mini_projects

SRA study group assignments

flexus

Contains the code for the Flexus cycle-accurate simulator, used in QFlex.

fos-proposals

:gift_heart: :penguin: Archive of GSoC proposals

gecko-dev-riscv

Read-only Git mirror of the Mercurial gecko repositories at https://hg.mozilla.org. How to contribute: http://bit.ly/contribute-code

intro_to_cv

SRA's seminar on Introduction to Computer Vision Fundamentals

libqflex

Contains the API used for interfacing between QEMU and Flexus.

logi7400

Logisim 7400 series integrated circuits library

logismtutorial

ninad-jangle

ninja3011.github.io

Portfolio website codebase for ninadjangle.com

obstacle-avoidance-using-ros-and-gazebo

A VJTI SRA problem statement

ombhilare999.github.io

https://omkarbhilare.tech/

portfoliosite

qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

qflex

Quick & Flexible Rack-Scale Computer Architecture Simulator

react-snippets

JPMC

react-todo

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

riscv-core

A customized RISCV core made using verilog

riscv-cpu-core

A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-simple-sv

A simple RISC V core for teaching

riscv_myth_workshop_dec20-karthikvnit

riscv_myth_workshop_dec20-karthikvnit created by GitHub Classroom

spi