Comments (4)
Thanks, I'll look into this today.
Quick question though, are you using the nvdiasasm from cuda 6.5? The
later versions are not compatible with maxas (the rest of cuda is, you just
need to overwrite the new version of nvdiasasm from the 6.5 release).
On Mon, Jan 4, 2016 at 12:51 AM, pr0metha [email protected] wrote:
Hi,
I've encountered two problems Both are possible to replicate with the
microbench application code by extracting the sass code and then trying to
insert the unmodified code into the kernel again:$ maxaspl -e microbenchcubin microbenchsass
$ maxaspl -i microbenchsass microbenchcubin1 When doing the insertion step, I get this:
Unable to encode instruction: MOV R1, c[0x0];It seems like something goes wrong in the extraction step here, because
the second argument should have two address fields This is what nvdisasm
returns: MOV R1, c[0x0][0x20];
The error is removed by adding [0x20]I've seen this problem in all kernels I've been trying to insert after
extracting them with maxas2 After modifying the MOV-instruction, this is the output from the
insertion step:
Unknown Code 0x10 (size:0)
Unknown Code 0x18 (size:0)
Unknown Code 0x00 (size:0)
Unknown Code 0x00 (size:0)
Modified microbench CTAID Offsets: '' => '0018,0028'
Modified microbench Exit Offsets: '00e8,0000,0000' => '0138'
Modified microbench ParamSecSize: 100 => 88
Kernel: microbench, Instructions: 0, Register Count: 10, Bank Conflicts:
0, Reuse: 211% (4/19)It seems strange that all these parameters are modified when the kernel is
unchanged And indeed, when running the application with the modified cubin
I get a segmentation fault I've tried different kernels with the same
result This doesn't happen if I roll back maxas to the commit before the
enhanced cubin support was added and try the exact same thing, so I guess
something goes wrong when the offsets are modifiedThanks!
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Reply to this email directly or view it on GitHub
#7.
from maxas.
Ok, submitted a fix. Let me know if that addresses your problems.
from maxas.
The MOV instruction problem is now eliminated. Thanks!
I was using the entire cuda-6.5 package. When doing that, the second problem still persists. However, if changing to cuda-7.5 with the 6.5-version of nvdisasm, everything works as expected. So I guess the second issue is not really an issue as long as no one uses cuda-6.5 (other than nvdisasm of course). :)
from maxas.
Yah, nvidia keeps making minor tweaks I need to adjust to. The new nvdisasm thing actually looks like a bug in that it outputs a bunch of useless and spurious brace characters into the assembly.
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Related Issues (11)
- missing copyright on sgemm64.sass HOT 1
- "It is illegal to set a Read-After-Write dependency on a memory store op", on unmodified sass HOT 12
- All the images in the SGEMM Walkthrough wiki are now broken links HOT 4
- for newbies: filling the missing bits in the documentation
- Why no updates?
- No Project or Solution files for microbenchmark
- What is Max64-8?
- TLDS RGBA instruction broken HOT 4
- Question about broadcast of shared memory in SGEMM wiki HOT 3
- microbench.cpp checks minor is >= 2. is this normal?
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