Ayush dixit's Projects
Bash script for adruino uno based microcontroller firmware extraction
128 bit aes implementation
Baremetal using KEIL U VISION for STM32F412ZGT6
Chisel: A Modern Hardware Design Language
CNN on fpga using verilog
Verilog Codes for various Design
draw
synchronous fifo verification using system verilog
Gui Based Make file generator
hardware software codesign
hardware for ai
Bram HLS
HLS codes for rtl generation
Build your hardware, easily!
lyrics search using api
for short messages delievery
Config files for my GitHub profile.
The Node.js website.
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
To make Real Time Clock using verilog
Mealy Machine Based Sequence Detector
Snake Robot using Adruino mega , IR sensor , ESP 32 CAM
Serial peripheral interface protocol using verilog and testbench
Lets Git started in the world of opensource, starting in the Zero To Mastery's opensource playground. Especially designed for education and practical experience purposes.