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aucstudents

beat-punch

Our project For the Embedded systems course.LiteBoxer clone, embedded systems project

blog

build-your-own-x

Master programming by recreating your favorite technologies from scratch.

candid

Identity Manager Service

ceaser-shift-encoder-and-decoder

this is a c++ implementation of the famous ciphering method (Caesar shift).

cmos_netlist_generator

generates the netlist code from a given boolean expression

cs-openfga

Commercial Systems OpenFGA

data-science

This is a collection of all my toolkits, functions, and solutions to some data science challenges that I solved

faiss

A library for efficient similarity search and clustering of dense vectors.

fcsann

fpga-calculator

a simple calculator the performs the basic mathematical operations on the Basys 3 board written in Verilog

gector

Official implementation of the papers "GECToR – Grammatical Error Correction: Tag, Not Rewrite" (BEA-20) and "Text Simplification by Tagging" (BEA-21)

gpu_programming_with_cuda

A repo for all my projects using nVidia CUDA toolkit for programming GPGPUs

ivy

The Unified Machine Learning Framework

k-map-simplifier

This is our implementation of the Kmap algorithm

livepatch-k8s-operator

commercial systems terraform repo config

livepatch-machine-charm

mina1460

Config files for my GitHub profile.

mina1460.github.io

networks-project

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

os-lab

python

:snake: Python Programs

real-time-voice-cloning

Clone a voice in 5 seconds to generate arbitrary speech in real-time

risc-v-processor

risc-v-processor-1

My project for the computer architecture course. Implementation of entire RISC-V ISA using Verilog to run on FPGA

search_engine_with_pagerank

an efficient search engine using the pageRank algorithm

simple_processor_simulator

A simulation of a simple multicore processor with shared memory that is thread safe with networking capabilities