mikecovrado / gettingverilatorstartedwithuvm

Simple UVM environment for experimenting with Verilator.

GettingVerilatorStartedWithUVM

This is a somewhat modified version of the source code for "Getting Started with UVM", a textbook by Vanessa Cooper of Verilab. Sources fetched from the Verilab webpage at https://www.verilab.com/post/getting-started-with-uvm-book on 2023-08-24. The goal of this repo is to create a simple, yet complete and realistic, UVM environment and get it compiling and running with Verilator.

Current status

0. Last tested with Verilator v5.018 on Ubuntu 22.04.
1. Not yet compiling (working on it).
2. Anything that is known to be not currently supported by Verilator is excluded with conditional compilation macros:

`ifdef VERILATOR
  // code that is not supported by Verilator...
`else
  // temporary work-around
`endif

Try it yourself!

First, install the latest version of Verilator. See https://verilator.org/guide/latest/install.html for details.

Second, create a shell environment variable UVM_HOME and clone the version of the UVM library from ChipsAlliance there.

$ export UVM_HOME="/location/of/UVM/lib"
$ git clone [email protected]:antmicro/uvm-verilator.git -b current-patches $UVM_HOME

The (somewhat brain-dead) script will get you started:

$ cd scripts
$ ./run_verilator.sh testname

gettingverilatorstartedwithuvm's Issues

UVM 2020.3.0 compile error

I try to compile UVM 2020.3.0 downloaded from https://github.com/accellera-official/uvm-core/releases/tag/2020.3.0. But I got error as below

 ./run_verilator.sh data0_test             
Using /tmp/uvm-core-2020.3.0/src to point at your UVM class library
%Error-PKGNODECL: /tmp/uvm-core-2020.3.0/src/base/uvm_coreservice.svh:379:42: Package/class 'type_id' not found, and needs to be predeclared (IEEE 1800-2023 26.3)
  379 |             m_hopper = uvm_phase_hopper::type_id::create("default_hopper");
      |                                          ^~~~~~~
                  /tmp/uvm-core-2020.3.0/src/base/uvm_base.svh:54:1: ... note: In file included from 'uvm_base.svh'
                  /tmp/uvm-core-2020.3.0/src/uvm_pkg.sv:58:1: ... note: In file included from 'uvm_pkg.sv'
                  ... For error description see https://verilator.org/warn/PKGNODECL?v=5.025
%Error: Exiting due to 1 error(s)
        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
./run_verilator.sh: line 148: ./verilator_obj_dir/Vuvm_pkg: No such file or directory

Is it there any requirement for UVM version?

Runtime error: `%Error: ../rtl/../tb/top.sv:20: Input combinational region did not converge.`

Summary

When attempting to run the run_verilator.sh script with ./run_verilator testname, verilation completes but a runtime error is produced when attempting to run the file. The full verilation output is in the attached logfile. Just the runtime error is displayed below.

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ ./run_verilator.sh testname #After previously verilating
Using /home/marcus/software/cu-fpga/include/uvm-verilator/src/ to point at your UVM class library
make: Entering directory '/home/marcus/software/GettingVerilatorStartedWithUVM/scripts/verilator_obj_dir'
make: Nothing to be done for 'default'.
make: Leaving directory '/home/marcus/software/GettingVerilatorStartedWithUVM/scripts/verilator_obj_dir'
- V e r i l a t i o n   R e p o r t: Verilator 5.029 devel rev v5.028-70-g4a589976
- Verilator: Built from 0.000 MB sources in 0 modules, into 0.000 MB in 0 C++ files needing 0.000 MB
- Verilator: Walltime 2.203 s (elab=0.000, cvt=0.000, bld=2.174); cpu 0.030 s on 48 threads; alloced 8.574 MB
UVM_INFO @ 0: reporter [UVM/RELNOTES] 
  ***********       IMPORTANT RELEASE NOTES         ************

  This implementation of the UVM Library deviates from the 1800.2-2017
  standard.  See the DEVIATIONS.md file contained in the release
  for more details.

----------------------------------------------------------------
Accellera:1800.2-2017:UVM:1.0

All copyright owners for this kit are listed in NOTICE.txt
All Rights Reserved Worldwide
----------------------------------------------------------------

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test data0_test...
%Error: ../rtl/../tb/top.sv:20: Input combinational region did not converge.
Aborting...
./run_verilator.sh: line 149: 139416 Aborted                 (core dumped) ./verilator_obj_dir/Vuvm_pkg +UVM_TESTNAME=data0_test

full_verilation_log.txt

Software Configuration

Verilator: verilator/verilator@4a58997

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ verilator --version
Verilator 5.029 devel rev v5.028-70-g4a589976

UVM Library: antmicro/uvm-verilator@2e667ac

marcus@fiora ~/software/cu-fpga/include/uvm-verilator/src $ git log --oneline -n1
2e667ac (HEAD -> current-patches, antmicro/current-patches) Remove rand specifier in dynamic arrays and queues

I also made a couple slight tweaks to the script (reduce error spam in UVM library, use all cores for verilation)

marcus@fiora ~/software/GettingVerilatorStartedWithUVM/scripts $ git diff
diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh
index 42975cf..c82e36c 100755
--- a/scripts/run_verilator.sh
+++ b/scripts/run_verilator.sh
@@ -116,7 +116,8 @@ DISABLED_WARNINGS="-Wno-DECLFILENAME \
                    -Wno-ZERODLY \
                    -Wno-SYMRSVDWORD \
                    -Wno-CASEINCOMPLETE \
-                   -Wno-REALCVT"
+                   -Wno-REALCVT \
+                   -Wno-SIDEEFFECT"
 
 # compile
  verilator \
@@ -128,7 +129,7 @@ DISABLED_WARNINGS="-Wno-DECLFILENAME \
      --error-limit 5 \
      --binary \
      --hierarchical \
-     -j 1 \
+     -j `nproc` \
      -Wall \
      $DISABLED_WARNINGS \
      +define+UVM_REPORT_DISABLE_FILE_LINE \

I've been trying to get my own UVM testbenches to work with verilator, and have run into the same runtime error there. Thought I'd give yours a try, but no luck apparently. Are you experiencing the same error?