Opening two DMA channels doubling signal width about rpio

[rogerjames99]

I am also seeing this issue. Here is some test code.

#!/usr/bin/env python

import RPIO
from RPIO import PWM
import time

PWM.setup()
RPIO.setup(25, RPIO.OUT, initial=RPIO.LOW)
PWM.init_channel(4)
PWM.init_channel(0)
PWM.add_channel_pulse(0, 25, 0, 100)
time.sleep(5000)

If you measure the output on a scope then the cycle time and pulse width are approximatery twice what they should be (i.e. cycle time 40ms rather than 20). If you comment out the PWM.init_channel(4) then the timing is correct.

Looking at the code, two dma engines are set up each consuming DMA_REQs. I am guessing that each individual engine is probably getting approximately half the DMA_REQs. I dont know how you can get round this. The split will probably not be exact as there is no guarantee at the microcode level that a particular channel will get any or all the DMA_REQs.

[camusdv]

I've tried to investigated this issue some time ago. From what I remember:

I have the same behavior with C code driver and with the python bindings. I did not see any problem in the code. Each DMA channel has its own control structure with DMA CBs and specific GPIO masking variables.

Moreover the signal width is doubled when more than 1 channel is initialized and using PWM clock. With PCM there is no problem.

I've checked PWM registers with 1 or multiple DMA channels and did not note any modifications. So clock frequency is just divided when starting new dMA channel with PWM without any changes in PWM registers (range) ... I'm missing something. I also did not see anything special requirements concerning PWM clock divisor (in the datasheet).

I would need some more information concerning the oscillator and derived clocks. (In a specific data sheet)

[rogerjames99]

#camusdv, I checked out w you said about the using the PCM fifo to source the DMA_REQs. I can confirm that the pulse width does not double on this case.

So to summarise.

1. With the default PWM fifo as the timing (DMA_REQ) source using more than dma channels (dma engines) will cause pulse increment to double thus doubling the length of the subcycle and any pulses in it.
2. Using the PCM fifo as the timing source having more than one dma channel works as expected.

So if you want to use more than DMA channel then you must use the PCM fifo as the clock source. Maybe the code should be modified to enforce this.

As to why this is happening I have no clue! I cannot see any difference in the broadcom spec between DMA_REQ line 5 and DMA_REQ line 2, on either the DMA engine side or the peripheral side.

[stewe93]

Is there any update about this issue? I cant scope it but my ESC fails to start when I use 2 DMA channels, with only one it works perfectly ( servo needs 20ms sub time, for the ESC I want to use only 3ms sub type thats why I need more dma channels)
OR
how can I use the PCM fifo instead PWM with python ?

[jboco]

Hi, is there any update about this issue. When I initialize a second PWM channel, the first channel goes to full width.