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article.eikonapi.rdp.python.optionstrategybacktesting

caravel_user_project

https://caravel-user-project.readthedocs.io

chainsaw

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

ddr_mgr_spartan3

Simple ddr manager working working with MIG, which is expected to work on spartan 3A starter

degreeone

A 5-stage pipeline MIPS32 CPU

example.eikonapi.python.optionsstrategies

fractal-fpga

A Mandelbrot set fractal accelerator implemented on Xilinx Spartan-3AN board with VGA display and zooming in by mouse

gowinddr3_axi4_spinalhdl

Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

gpt4free

decentralising the Ai Industry, free gpt-4/3.5 scripts through several reverse engineered api's ( poe.com, phind.com, chat.openai.com, phind.com, writesonic.com, sqlchat.ai, t3nsor.com, you.com etc...)

notebook

nova

证券投资交易分析系统程序及文档资料

opbasm

Open PicoBlaze Assembler

optionsuite

Option and stock backtester / live trader

optopsy

A nimble options backtesting library for Python

ping-pong-fpga

Basic ping-pong game written in Verilog runs on Xilinx Spartan3AN starter kit

qtpynodeeditor

Python Qt NodeEditor (qtpy, PyQt5, PySide)

rt

A Full Hardware Real-Time Ray-Tracer

scipybook2

Python科学计算(第2版) 的源代码

sicp_solution

Contain all the solutions to SICP exercises

smartverilog

Perl script to instantiate modules from mutiple .v .sv files and connect signals among them,

some-investment-books

spinalhdl_cnn_accelerator

CNN accelerator implemented with Spinal HDL

tetris_spinalhdl

Tetris game in SpinalHDL

tos-and-thinkscript-snippet-collection

trading_evolved

Trading Evolved book code

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

ztachip

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.