Name: Max Baker
Type: User
Bio: Designer of strange chips : rad-hard, space-timed, and side-channel protected. VLSI and ASIC digital design. Recovering SW engineer and author of Netdisco.
Location: San Francisco, California
Blog: https://www.linkedin.com/in/maxbaker
Max Baker's Projects
Adventures in Minecraft Windows PC Starter Kit
A small tool to look up ISBN numbers and create a CSV file from a list of book suggestions. For Goodreads
Using Espresso logic minimizer to RE bitstream assignments of a CPLD
Person .rc files and such
Mikrotik configuration files for a moderately complex home network with managed access points, FTTH with authentication, multiple ISPs with failover, secure DNS, and VLANs.
Mediawiki scraper: all your wiki articles in one highly compressed ZIM file
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Digital timing diagram editor