- π Hello! Iβm @mankelly.
- π Iβm interested in Embedded System Design using Verilog/SystemVerilog and Embedded System Software development.
- π± Iβm currently learning CPU design and VHDL to expand my HDL library.
- ποΈ Iβm looking to collaborate on Embedded Systems projects.
- π« How to reach me? Contact me on LinkedIn!
mankelly Goto Github PK
Name: Manuel Kelly
Type: User
Bio: FPGA Engineer focusing in Digital Communication and Machine Learning.