manalshah Goto Github PK

5-stage-32-bit-add-sub

Single Precision(32-bit) five stage Floating Point Adder and Subtractor.

ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

awesome-deep-learning-papers

The most cited deep learning papers

cmpe242

SJSU CMPE 242: Embedded Linux Hardward/Software

data-science-blogs

A curated list of data science blogs

design-and-verification-of-ddr3-memory-controller

The memory model was leveraged from micron.

freecodecamp

The https://freeCodeCamp.com open source codebase and curriculum. Learn to code and help nonprofits.

machine-learning-for-software-engineers

A complete daily plan for studying to become a machine learning engineer.

multiplier

Signed Binary Multiplier & Divider Circuit(64-bit )

nios2-altera

Nios II Processor-Altera

optix_advanced_samples

pattern_classification

A collection of tutorials and examples for solving and understanding machine learning and pattern classification tasks

python_packer

Packs Python projects into single Pyhton file for easy re-distribution

twitter-stock-sentiment

Stock market sentiment analysis on twitter

unmanned-crane

A gesture controlled unmanned vehicle whose motion in various directions can be controlled by human gestures.

uvmreference

Reference examples and short projects using UVM Methodology

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

walnut

work in progress towards an artificial general intelligence(AGI) for everyone