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100-days-of-ml-code

100 Days of ML Coding

100-days-of-rtl

This is the repository for checking out the codes , testbenches and simulation results of my 100 days of RTL journey where I continually learn about various digital circuits

100-days-of-rtl-code

100-days-of-rtl2

Salutations to my fellow VLSI enthusiasts! I'm Kanna Akshay, a fan of VLSI who designs RTL in Verilog HDL using Intel's Quartus Prime 17.1 and ModelSim for simulation and synthesis. Come along for the ride as 100 days are devoted to perfecting RTL design and developing Verilog abilities.

100daysrtl

floating-point-alu-in-verilog

32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

projects

resume-projects

sixstageriscpipeline

sv-tutorial

SystemVerilog Tutorial

tt06-sar

SAR ADC on tiny tapeout

vlsi-design-digital-system

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

vlsi-fundamentals-education-kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor