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12306

12306智能刷票，订票

8051

FPGA implementation of the 8051 Microcontroller (Verilog)

8051-1

8051 core

arm9-compatible-soft-cpu-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

awesome-cpus

All CPU and MCU documentation in one place

cores

Various HDL (Verilog) IP Cores

django-cms

The easy-to-use and developer-friendly CMS

djangoblog

🍺基于Django的博客系统

e200_opensource

The Ultra-Low Power RISC Core

easynote

A simple project which about a note， bill， inventory and so on.

easynote1.3

Third edition of EasyNote

erpnext

Open Source ERP built for the web

gitchat-mvue

hello_world

Hello world!

learncandcppdiary

学习C和C++笔记整理

learnpythondiary

Python学习笔记整理

learnwebdiaries

A Web Learning Diaries From all of My Path

lzclizechen.github.io

mips-cpu

MIPS CPU implemented in Verilog

openbilibili

qemu

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

r8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

risc-v_spec

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

sis-base-edition-python

Student Information System

sis-updated-version

一个升级版的SIS。基于Python。

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

tetrisgame

俄罗斯方块游戏开发教程实例代码

turbo8051

turbo 8051

uvm_axi

uvm AXI BFM(bus functional model)