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Name: 时光之箭

Type: User

Bio: 专注于芯片技术，兼顾金融交易

时光之箭's Projects

any-point-dft

Algorithm and VLSI implementation of any point DFT/FFT-Matlab/C/Verilog

biriscv

32-bit Superscalar RISC-V CPU

core_dbg_bridge

UART -> AXI Bridge

ctp-future-option

基于上期技术CTP平台，C++设计，国内期货期权交易程序

ctp-stock-option

基于上期技术CTP平台，C++设计，国内股票期权交易程序

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

iverilog

Icarus Verilog

ptpd

PTPd official source - master branch a.k.a. trunk

riscv

RISC-V CPU Core (RV32IM)

riscv-linux

RISC-V Linux Port (supporting RV32IM - CPUs without atomic extensions)

riscv-linux-boot

Trivial RISC-V Linux binary bootloader

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

riscv_soc

Basic RISC-V Test SoC

shared-resource

存放一些开源小型软件安装包之类的资源，供其它项目使用。

tsn-soc

用于时间敏感网络TSN(Time-Sensitive Network)的SoC设计

tsn-switch

用于时间敏感网络TSN（Time-Sensitive Network）的Switch设计

uart

UART的Verilog HDL实现，适用于各种FPGA/ASIC设计

verilator

Verilator open-source SystemVerilog simulator and lint system

xge-ptpv2

用于10G以太网的PTPv2硬件引擎设计，Verilog HDL描述

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