lvhz123,github

955.wlb

955 不加班的公司名单 - 工作 955，work–life balance (工作与生活的平衡)

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

ddr2_controller

DDR2 memory controller written in Verilog

ddr4memorycontroller

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

design-and-verification-of-ddr3-memory-controller

The memory model was leveraged from micron.

e200_opensource

The Ultra-Low Power RISC Core

nerdtree

A tree explorer plugin for vim.

openc910

OpenXuantie - OpenC910 Core

processor-uvm-verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

qspiflash

A set of Wishbone Controlled SPI Flash Controllers

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

sdram-controller

Verilog SDRAM memory controller

systemverilogreference

training labs and examples

testbenchgenerator

Generate SystemVerilog/UVM block level testbench setup with python script

the-python-code-implements-aircraft-warfare

python代码实现飞机大战

uvm_auto

uvm auto generator

uvm_tb_gen

generate UVM testbench using python

uvmpy

UVM in Python for IC Verification

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-uart

Verilog UART

vundle.vim

Vundle, the plug-in manager for Vim

wbuart32

A simple, basic, formally verified UART controller

wujian100_open

IC design and development should be faster，simpler and more reliable

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