lswang2 Goto Github PK

anysoftkeyboard

Android (f/w 1.5+) on screen keyboard for multiple languages (chat https://gitter.im/AnySoftKeyboard)

base

binutils-gdb

Binutils and gdb fork for OpenRISC

build-tools

bytom

Official Go implementation of the Bytom protocol

cores-swerv

SweRV EH1 core

ctu-can-fd

This is a mirror repository for official CTU CAN FD repository:

daisho

SuperSpeed USB 3.0 FPGA platform

de0_test

OpenRISC multicore SoC for De0 Nano

dockerize-eda

[WIP] Dockerize Synopsys/Cadence EDA tools

effective-python

Learn and summarize 'Effective Python'

gdt

hardware-matrix-multiplication-accelerator

Hardware Matrix Multiplication Accelerator (Verilog RTL)

liberty-parser

litedram

Small footprint and configurable DRAM core

litex

Build your hardware, easily!

lswang2.github.io

A github pages / jekyll powered wiki. Readme and demo: (http://drassil.github.io/git-wiki)

lswang2.github.io_old

A simple Jekyll theme for showcasing your work, emphasis on whitespace, transparency, and helvetica.

ml-ahb-gen

A Verilog AMBA AHB Multilayer interconnect generator

or1k_toolchain_howto

orpsoc

[abandoned fork] OpenRISC Reference Platform SoC

python-cookbook

Code samples from the "Python Cookbook, 3rd Edition", published by O'Reilly & Associates, May, 2013.

python-deltasigma

A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

rocket-chip

Rocket Chip Generator

securenotepad

A simple, bare-bones, no-frills note taking app for Android.

sourceafis-java

Fingerprint recognition engine for Java that takes a pair of human fingerprint images and returns their similarity score. Supports efficient 1:N search.

swd_programing_sram

Programming internal SRAM over ARM Cortex M3 SWD

systemverilog-implementation-of-ddr3-controller

The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.

test