Comments (1)
This was due to MMCM loosing lock and resetting some modules. This is expected to happen, but the wishbone registers should keep their values so after reset the FS clock domain goes back to the previous values (and not the reset value).
This is fixed in commits lnls-dig/dsp-cores@8aad355 and lnls-dig/dsp-cores@9e92f2b
from bpm-gw.
Related Issues (20)
- [fmc250m_4ch] Expose ADC delay functions enhancement
- [dbe_bpm2] pll_status_i unconnected
- [trigger] Trigger IFACE has typo on register assingment
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- [MONIT1/MONIT tag delay] delays are applied as "ADC clock cycles" granularity
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