Comments (3)
Yep, fair criticism. I ran this through godbolt, looks like it's coming down from the frontend as a 1-bit XOR:
# Machine code for function invert: IsSSA, TracksLiveness
bb.1.entry:
liveins: $a
%1:_(s8) = COPY $a
%2:_(s8) = G_ASSERT_ZEXT %1:_, 1
%0:_(s1) = G_TRUNC %2:_(s8)
%3:_(s1) = G_CONSTANT i1 true
%4:_(s1) = G_XOR %0:_, %3:_; example.c:3:12
%5:_(s8) = G_ZEXT %4:_(s1); example.c:3:5
$a = COPY %5:_(s8); example.c:3:5
RTS implicit $a; example.c:3:5
# End machine code for function invert.
Our legalizer is lowering it to the following select:
# Machine code for function invert: IsSSA, TracksLiveness, Legalized
bb.1.entry:
liveins: $a
%1:_(s8) = COPY $a
%2:_(s8) = G_ASSERT_ZEXT %1:_, 1
%0:_(s1) = G_TRUNC %2:_(s8)
%3:_(s1) = G_CONSTANT i1 true
%6:_(s1) = G_CONSTANT i1 false
%4:_(s1) = G_SELECT %0:_(s1), %6:_, %3:_; example.c:3:12
%7:_(s8) = G_CONSTANT i8 1
%8:_(s8) = G_CONSTANT i8 0
%5:_(s8) = G_SELECT %4:_(s1), %7:_, %8:_; example.c:3:5
$a = COPY %5:_(s8); example.c:3:5
RTS implicit $a; example.c:3:5
# End machine code for function invert.
This is because 1-bit XORs are just how the IR happens to represent negation of boolean flag values, and it's usually better to lower those to control flow (which usually folds away to nothing) than to widen to 8 bits, XOR, then truncate.
But, in this case, the 1-bit XOR is immediately zero-extended (ZEXT) to 8 bits, so we might as well just compute an 8-bit XOR. Should be a relatively simple thing to fix.
from llvm-mos.
Fixed by 2b1d155
from llvm-mos.
Had to revert the fix to this, as it causes a pretty severe regression elsewhere.
This will take some doing; the game here is surprisingly tricky, and I don't fully understand all the behavior of all the pieces yet.
from llvm-mos.
Related Issues (20)
- Support assembler sources in ca65 format
- Lower mem intrinsics to loops
- G_OR prevents selection of addressing mode HOT 1
- Don't copy single-use strings to the zero page
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- Compilation failure on MacOS w. Apple silicon HOT 11
- Builder for Apple Silicon
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- [65C816, 65CE02] Long branch instructions not supported HOT 2
- ld.lld: error: undefined symbol: __rc4 to __rc24 HOT 3
- Missing G_SBC commutation for equality checks HOT 1
- [Assembler] Improved ergonomics for 65816 (and other) subtargets HOT 14
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- Compiler crashes when try to access a member variable of a class through inline assembly HOT 5
- Declaration order of member variables has a big impact on code optimization HOT 1
- Surface error messages for inline assembly
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from llvm-mos.