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axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

charm

CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

high-level-synthesis-flow-on-zynq-using-vivado-hls

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

image-store

lc-3

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

low-pass-filter

pytorch-pretrained-vit

Vision Transformer (ViT) in PyTorch

skrskr

The second place winner for DAC-SDC 2020

skynet

trans-fat

An FPGA Accelerator for Transformer Inference

transformer_core

a student trainning project for HLS and transformer

vitcod

[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design

wislearning

zipcpu

A small, light weight, RISC CPU soft core