leonui Goto Github PK

algorithms

Bug-tracking for Jeff's algorithms book, notes, etc.

asic-design-roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

awesome-cheatsheets

超级速查表 - 编程语言、框架和开发工具的速查表，单个文件包含一切你需要知道的东西 :zap:

awesome-python-login-model

😮python模拟登陆一些大型网站，还有一些简单的爬虫，希望对你们有所帮助❤️，如果喜欢记得给个star哦🌟

brecq

Pytorch implementation of BRECQ, ICLR 2021

calibtip

Improving Post Training Neural Quantization: Layer-wise Calibration and Integer Programming

convnext

Code release for ConvNeXt model

dnn-accelerator

hdlgen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

hello-streamit

micronet

micronet, a model compression and deploy lib.

models

Models and examples built with TensorFlow

nyuziprocessor

GPGPU microprocessor architecture

pytorch-playground

模型量化工程 Base pretrained models and datasets in pytorch (MNIST, SVHN, CIFAR10, CIFAR100, STL10, AlexNet, VGG16, VGG19, ResNet, Inception, SqueezeNet)

pytorch_memlab

Profiling and inspecting memory in pytorch

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

tensorflow-course

Simple and ready-to-use tutorials for TensorFlow

theano_alexnet

Theano-based Alexnet

verilogpp

veripy

VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, various code generation plugins and configurable code generation. The VeriPy Wiki has more the detailed documentation.