krraushan Goto Github PK
Name: Kumar Raushan
Type: User
Company: Shri Mata Vaishno Devi University
Twitter: KR_RaushanParag
Location: Gaya,Bihar
Name: Kumar Raushan
Type: User
Company: Shri Mata Vaishno Devi University
Twitter: KR_RaushanParag
Location: Gaya,Bihar
#100DaysofMLCode Challenege
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
Frontend Masters Bootcamp
Source code for Django For Beginners
Image Processing Toolbox in Verilog using Basys3 FPGA
5-stage pipelined 32-bit MIPS microprocessor in Verilog
A python project for checking plagiarism of documents based on cosine similarity
Command-line tool that instantly fetches Stack Overflow results when an exception is thrown
Unicompiler Internship Task Submission
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