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kmd178's Projects

digital_systems_lab1_7segmentdisplay icon digital_systems_lab1_7segmentdisplay

Ο στόχος της πρώτης εργαστηριακής εργασίας είναι η υλοποίηση ενός οδηγού των τεσσάρων ενδείξεων 7-τμημάτων LED της πλακέτας Spartan 3, για να επιτευχθεί η περιστροφική παρουσίαση ενός μηνύματος μεγέθους 16 χαρακτήρων.

digital_systems_lab2_uart icon digital_systems_lab2_uart

Implementation of serial data transfer between two distinct systems running different clocks using the Universal Asynchronous Receiver&Transmitter protocol. The system consists of a UART transmitter and a UART reciever with a single serial connection between them. The bitstream transmitted is utilized by the reciever to drive the 7segment display implemented in the previous assignment.

digital_systems_lab3_vga icon digital_systems_lab3_vga

Implementation of a Video Graphics Array Controller/Driver. The goal is to successfully drive a typical monitor and display an image in it. For the purpose of continues representation through the VGA port, part of the internal RAM of the FPGA unit used will be assigned as Video RAM (VRAM) of the driver. The suggested sample image for the testing of the aforementioned driver is the typical red, blue, green,black horizontal stripes separated repeatedly by white stripes. The black stripes part is also repeatedly vertically overlapped by a red,green,blue vertical stripe.

digital_systems_lab4_lcd icon digital_systems_lab4_lcd

Implementation of a Liquid Crystal Display driver. The goal is to experiment with the various functions of the Spartan3E's onboard LCD. The suggested sample string for testing the aforementioned driver is the typical message ABCDEFGHIJKLMNOPabcdefghijklmno , the last(32nd) character being a circularly rotating single digit cursor. The message is registered in the BRAM memory of the FPGA and the LCD driver is utilized to continuously drive it in the LCD refreshed in 1 second intervals (including the display of the rotating cursor implementation). Placement of the BRAM should be preconfigured to take place in the uppermost left part of the available memory in the Spartan3E board.FPGAs like the Spartan3E board typically have a preconfigured synthesizable processor to drive the LCD and make the implementation less complicated . Because the use of the above processor can utilize a big portion of the LUTs and registers of the FPGA, it can prohibit functionallity or increase the hardware requirements of an FPGA implementation. This project involves direct implementation of some of the LCD driver's fanctions in the main system tailored for minimum footprint in the available resources.

embedded_systems_lab1_gray icon embedded_systems_lab1_gray

Functional simulation and implementation of a GRAY counter in Verilog using the Xilinx Vivado toolset and testing the design on the Zynq-7000 Zedboard digital system development platform.

embedded_systems_lab2_arm icon embedded_systems_lab2_arm

Testing software part of an FPGA-based System On Chip, using Vivado and IP Integrator to create a simple ARM CortexA9 based processor design targeting the ZedBoard development board. Using the IPIntegrator to create the hardware block diagram and the SDK (Software Development Kit) to create software applications verifying the hardware functionality and profiling the code. The interrupt facilities of the CPU are used to count the number of times Zedboard buttons have been pushed by the user and their value is writen to the desktop monitor through a UART connection to the board.

embedded_systems_lab3_customip icon embedded_systems_lab3_customip

Experimenting with creating and adding a custom peripheral to the embedded system. The hardware for the peripheral will connect to the AXI4 bus and the application will be coded to communicate to this peripheral. For the first implementation the application software reads the 8 switches of the Zedboard and turns on/off the corresponding LEDs. For the second implementation a Gray Code hardware accelarator completed in a previous project is used as an IP through the AXI4 interface with some extra software&harware code to control/monitor its functionality on the Zedboard.

embedded_systems_lab4_hw_sw_acceleration icon embedded_systems_lab4_hw_sw_acceleration

FPGA fabric can be used to implement hardware accelerators to offload computationally demanding tasks from the CPU. A really simple software application is developed in the ARM Cortex-A9 processor that will be used to profile and assess its performance footprint. Software running on a processor, no matter how well optimized it is, is slower than a hardware accelerator implementing the same functionality. Based on the outcome of SW profiling the computationally intensive parts of the application will be implemented as a hardware accelerator to further improve performance.

embedded_systems_sobel_filter__blockdesign-sdk icon embedded_systems_sobel_filter__blockdesign-sdk

Based on a SW version of a Sobel filter written in C, using the Vivado HLS (High Level Synthesis) tool a hardware accelerator is build reducing the function's execution time on an ARM processor to the minimum using various optimizations through code directives. The optimizations are tested individually for their additional performance gains. Software running on a processor, no matter how well optimized it is, is slower than a hardware accelerator implementing the same functionality. Translating the functionality of a computationally intensive function to a HW Description language using all the available advantages HW parallelism and flexibility has to offer can be a really time consuming and often repetitive feat.

embedded_systems_sobel_filter_hls icon embedded_systems_sobel_filter_hls

Various HLS directives and code restructuring is used to increase performance on the output Sobel accelerator IP (mostly at the expense of extra area) . The following methods are tested for their effectiveness: Loop unrolling and pipeling, avoiding conditionals in the source code (if-then-else) and replacing short conditionals, Determining which operations are in the critical path and try to circumvent their effect by running them in parallel or even replacing them with cheaper (even approximate!) operations. Re-writing source code to improve bandwidth and solve reduntant memory accesses.

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