Comments (1)
Addressed in the discussion in #13.
from aes-processor.
Related Issues (20)
- Investigate "0-in" setup for emulation assertion usage HOT 1
- Investigate additional SCEMI Pipes options HOT 1
- Create Need For Speed Proposal HOT 7
- Implement code coverage HOT 4
- Modify Transactor to test all 3 AES version in parallel HOT 2
- Improve usage of valid bit propogation through modules HOT 3
- Enable Questa Simultion Profiling HOT 1
- Add capability to top level testbench for "seeded tests" HOT 4
- Update HVL testbench to do directed and then seeded testing HOT 3
- Create decoder->encoder in Transactor to utilize other data in the test vector HOT 1
- Change generated vector format HOT 4
- ExpandKey test bench produces a stack trace HOT 3
- Modify make file to only run top level testbench once HOT 1
- Update block diagrams HOT 3
- Compile time selection to infer RAM or not for LUTs HOT 1
- Modify seeded testing to use encrypted data HOT 1
- Investigate other ways to transfer data to the emulator HOT 2
- Add additional assertions HOT 1
- Add additional background information to the final paper HOT 2
- Add assertion negative testing HOT 2
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