Comments (1)
You have precisely the idea of how it is supposed to work. I think it is pretty nice as well, and is probably closer to how hardware like this might be built.
This is definitely a bug. From what I found it looked like OP_JSR was actually the problem.
lc3-alt.cpp: In function ‘void ins(uint16_t) [with unsigned int op = 4]’:
lc3-alt.cpp:282:23: warning: ‘r1’ may be used uninitialized in this function [-Wmaybe-uninitialized]
reg[R_PC] = reg[r1];
JSR has two modes, and it looks like neither of our programs use the second mode which is why we didn't notice it.
I like the constexpr
and will add it to opbit
to emphasize what should be going on.
I won't add it to the conditional, as that requires C++17, and requires some other changes for clang.
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Related Issues (17)
- Tests for testing correct implementation? HOT 6
- Some error in section LDI? HOT 1
- Typo? HOT 3
- Wow thank you so much! HOT 1
- Going Branchless HOT 5
- Shouldn't sign_extend() return a int16_t instead of a uint16_t? HOT 4
- Is Gonna Work? HOT 1
- Question about using uint16 HOT 2
- Missing fflush? HOT 1
- Condition flags aren't updated when reading keyboard characters
- bug in PUTSP trap implementation? HOT 7
- TRAP instruction should modify R7
- Typo: it seems the `break` keyword in JSR(R) implementation is redundant
- Need help regarding bitwise AND HOT 1
- Changes to the LEA and TRAP instructions in the Third Edition HOT 3
- The C and C++ files are missing HOT 2
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