spi slave in hw => dout_vld no creating '1' value about spi-fpga

[jakubcabal]

Hi,

can you please capture the following signals using signaltap?
spi_clk_fedge_en, spi_clk_redge_en, bit_cnt, last_bit_en

[imuguruza]

It looks like fedge is not being detected:

I will have closer look...

edited the capture I have uploaded was wrong...
Now I am sending just 8 bits, the "standard" data field

[jakubcabal]

Hi,

it looks like a problem with reset. spi_clk_reg is still in low, so is probably still in reset state.
What is the RST signal value? My implementation uses reset active in high.

[imuguruza]

Hey you were right, I assigned the reset pin into an input not used.
So the value read was '1'. not allowing a proper function of the design.
I have assigned the reset to '0' value and now is working fine.
Thanks for your support!