ahb-to-apb-bridge-verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

aliengame

basicsr

Open Source Image and Video Restoration Toolbox for Super-resolution, Denoise, Deblurring, etc. Currently, it includes EDSR, RCAN, SRResNet, SRGAN, ESRGAN, EDVR, BasicVSR, SwinIR, ECBSR, etc. Also support StyleGAN2, DFDNet.

basicsr-docs

cellift-meta

All the tools you need to reproduce the CellIFT paper experiments

chisel-rv32

chisel-rv32

da_puf_library

Defense/Attack PUF Library (DA PUF Library)

dift-test-sw

Test SW for the RISC-V Pulpissimo CV32E40P platform extended with DIFT

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

grow-rv32

This is an experiment for lab's members, aiming to design an RV32 SoC. In the future, we will continuously add the desired functions to it.

handyfigure

HandyFigure provides the sources file (ususally PPT files) for paper figures

howtocook

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Chinese only).

jacobojin

jacobojin.github.io

This is my personal homepage project

papers-we-love

Papers from the computer science community to read and discuss.

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

risc-v-on-pynq

RISC-V Integration for PYNQ

riscv-dift

riscv-on-pynq-z2

This repo is to inplemente the riscv soc on the xilinx pynq-z2 board

rocket_chip_vpu

soric_project

Source-Opened RISCV for Crypto

uart-ip-core16550a-verification-uvm

The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry-standard National Semiconductors’ 16550A device.

uart16550

verilog-sha-family

FPGA implementation of SHA1/SHA224/SHA256/SHA384/SHA512.

zju-icicles

浙江大学课程攻略共享计划