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attnsleep

[TNSRE 2021] "An Attention-based Deep Learning Approach for Sleep Stage Classification with Single-Channel EEG"

bosch-bno055-stm32

Library for the Bosch BNO055 Sensor based on and used with the STM32-HAL.

build-your-own-x

Master programming by recreating your favorite technologies from scratch.

connectedhomeip

Matter (formerly Project CHIP) creates more connections between more objects, simplifying development for manufacturers and increasing compatibility for consumers, guided by the Connectivity Standards Alliance.

deepsleepnet

DeepSleepNet: a Model for Automatic Sleep Stage Scoring based on Raw Single-Channel EEG

dfformer

Towards Domain Free Transformer for Generalized EEG Pre-training

drowsinessdetection

gymnasium

A standard API for reinforcement learning and a diverse set of reference environments (formerly Gym)

idm-vton

IDM-VTON : Improving Diffusion Models for Authentic Virtual Try-on in the Wild

imu_stm32_discovery

Using Inertial Measurement Unit integrated with STM32 Discovery to measure orientation and pass the data to Matlab for integration by Kalman filter and further analysis.

mcsleep

Multichannel Sleep Spindle Detector for sleep EEG

mediapipe

Cross-platform, customizable ML solutions for live and streaming media.

mediapipeposeestimation

mpu9255-quaternion-ahrs-stm32

Quaternion Based AHRS Estimation Using MPU9250 and STM32G431

openpiton_prototyping

pulse

PULSE: Self-Supervised Photo Upsampling via Latent Space Exploration of Generative Models

pylance-release

Documentation and issues for Pylance

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

sleep-eeg-event-detector

Sleep EEG Event Detector (SEED) model, a deep learning-based detector of sleep spindles and K-complexes

sleepecg

Sleep stage detection using ECG

ts-tcc

[IJCAI-21] "Time-Series Representation Learning via Temporal and Contextual Contrasting"

tsleep

Automated Sleep Stage Scoring using Deep Learing

zipcpu

A small, light weight, RISC CPU soft core

ztachip

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.