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arty-a7-35-gpio

atg-parse

Python script for converting binary AXI Traffic Generator coe files to hex table

checkespeare

Literature Collection in F-1 Check University

cmsis

Cortex Microcontroller Software Interface Standard

dotfiles

dot files for macos and linux systems

enceladus

Get Netease music lyrics + timestamps with Python 3

erriapo

Getting rid of the laggy epub readers on Windows

fdu-hackthon-2017

fusionaccel

RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.

gaia

Generate UVM testbench framework template files with Python 3

gigantes

A greedy snake game running on Cyclone IV FPGA. Array LEDs Required.

git-clean

simple scripts to cleanup github repo

gunrock

High-Performance Graph Primitives on GPUs

iapetos

An imitation of the Binding of Isaac with cocos2dx

ihex2vmf

Python script for converting Intel Hex memory file to Micron VMF

rhea

A crawler framework with PyQt5 GUI

rmii_arty

RTL RMII Ethernet Implementation on Arty A7

rmii_kintex

RTL RMII Ethernet Implementation on Kintex 7

squeezenet

SqueezeNet: AlexNet-level accuracy with 50x fewer parameters

tarvos

macOS Mojave on Kaby Lake XPS13 9360

tethys

C++ standard library for rogue-like & SLG game developing

thor

An FPGA based BJT test program, including FPGA RTL programs and MATLAB GUI.

tracing-android

A social and game app based on map service on Android

verilog-dvp

verilog dvp transceivers, TX implemented on Arty A7-35T, RX implemented on Basys 3 with direct VGA output

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-fx3slvfifo

Control Cypress FX3 Slave FIFO with FPGA

verilog-mii

Example platform for Xilinx AXI_EthernetLite (MII) on Arty A7-35T, including active TX driven by AXI Traffic Generator and dummy RX

verilog-rmii

Example platform for Xilinx MII_to_RMII IP on Arty A7-35T, including ethernet RX and TX

vivado-build-system

Vivado build system

wonton

Wonton