Comments (2)
X-propagation for simulation? I regularly assign things to X in non-synthesisable code, particularly defaults in sequential case statements to allow for x-propagation.
FPGA synthesis optimisation? Some tools understand assignment to X as don't care and thus don't infer latches.
There is a lint error here though as rxReg is 4-bit.
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Yes, there are a number of width assignment errors like that one, probably unimportant. I could make a PR for them if Ijor is interested.
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Related Issues (13)
- HALT input signal. HOT 4
- Not compatible with iVerilog HOT 18
- Possible issue with UNLK HOT 2
- How to request the bus? HOT 6
- Hidden bug HOT 15
- subq instruction bug HOT 2
- Enumerated value used on its own in if condition HOT 2
- Usage of synthesis on / off HOT 6
- Zolt HOT 1
- Warnings by GoWin IDE HOT 2
- Is BGACKn behavior correct? HOT 4
- SystemVerilog to Verilog conversion seems to be successful HOT 3
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