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aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

apb

APB Logic

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

biriscv

32-bit Superscalar RISC-V CPU

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cmsdk_ahb_busmatrix

practice configure AHB-Lite bus protocol

common_cells

Common SV components

core_spiflash

SPI-Flash XIP Interface (Verilog)

cores

Various HDL (Verilog) IP Cores

cores-swerv

SweRV EH1 core

cryptech

Collection of CrypTech repos to making cloning easier.

eda-tools

Verilog Gate-Level Studio

edalize

An abstraction library for interfacing EDA tools

frv2100

PulseRain FRV2100 RISC-V Core

hackdac_2018_beta

The SoC used for the beta phase of Hack@DAC 2018.

hyperram

simple hyperram controller

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

iob-soc

RISC-V System on Chip Template

kryon

FPGA,Verilog,Python

libuvc-for-vs2017

n3-minized

N3Z design of Nicola cave radio for the minized

neta

netlist-graph

Java library for parsing and manipulating graph representations of gate-level Verilog netlists

netlist-verilog

Netlist and Verilog Haskell Package

nlviewer

verilog netlist viewer and analyzer

openfpga

Open FPGA tools

openip

Open source IP collection

openocd

Spen's Official OpenOCD Read-Only Mirror (no pull requests)

opentitan

OpenTitan: Open source silicon root of trust