Comments (6)
hunterlew
commented on July 3, 2024
您好，mult_16是有符号的16位乘法核，直接在ISE中调用即可，工具将自动生成单独的目录结构。受大小限制没有上传。
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gamersover
commented on July 3, 2024
哦，是这样啊，因为我是用Altera的FPGA做的，我现在想用你的程序做modelsim仿真，需要安装ISE后，再调用modelsim仿真吗？还是说可以直接使用Quartus调用modelsim仿真，只要有mult_16模块就可以了？
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hunterlew
commented on July 3, 2024
一样的，有乘法核就行。另外，分享的程序仅作为参考，网络参数需要根据自己的实际模型导入，需要一定的时间。目前没有较好的方法。
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gamersover
commented on July 3, 2024
恩，我也大致看了一下你的代码，发现还有其他模块没有上传到github，不过还是有很大参考价值，多谢了
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wxbbuaa2011
commented on July 3, 2024
为什么用乘法核，而不直接用*，综合使用DSP48E呢？能加个微信吗？你建个群大家进去交流下呢？我的微信：a793625982
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zhangqingbo1
commented on July 3, 2024
@hunterlew 大佬，建个微信群吧，好好请教下
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Related Issues (19)
- 楼主可否分享一下论文连接，拜托拜托 HOT 1
- 有问题请教，已发邮箱
- 烧录板子
- Developing with my CNN
- Help regarding compiling the source files HOT 1
- 反向传播代码
- 各个参数配置能给出么，感谢！
- 求问两个例化是什么意思
- bias_mult乘法器
- 例化模块
- 你好，跑了一下，少了很多模块，比如xil_defualtlib.mult16，xil_defualtlib.im_in。这些东西从哪里找，请问能上传一下么 HOT 4
- 模块说明 HOT 3
- How to configure multiplier ,rom and ram? HOT 2
- 关于数据读取m_conv_3_ram HOT 2
- 使用的芯片是啥 HOT 5
- 方便私下交流一下吗？ HOT 2
- 楼主能不能分享一下论文链接呀 HOT 1
- 池化层 HOT 1
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