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6-stages-pipelined-risc-v

A 32 bit low power pipelined RISC processor from Computer Architecture subject in HCMUT

ahb_gen_201

An AHP Bus Generator From my Thesis Proposal in HCMUT

asyncfifo

An asyncchronous FIFO

axi4_bus

An AXI Bus Design - a part from Vanguard SoC project

basic-knowledge

This contains all the references links from different projects

cache-coherence

hungbk99

lpae

mmu

renas-mcu

Bachelor Thesis

rvs192-cpu

A 32-bit RISC-V CPU using SystemVerilog from my Design Project in HCMUT

single-precision-floating-point-unit

A Single Precision Floating Point Unit Using SystemVerilog from Advanced Digital Techniques subject in HCMUT

spi_apb

A SPI design (supporting APB interfaces) using Systemverilog from VG_CPU project

sva_gen

An SVA generator from .CSV file using Cshell