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aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

asic--an_asic-based_architecture_of_fast_fourier_transform

des_asic

Implementation of a hardware DES module in Verilog

e200_opensource

The Ultra-Low Power RISC Core

ethernet_10ge_mac_sv_uvm_tb

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

h265-encoder-rtl

nyuziprocessor

GPGPU microprocessor architecture

oh

Verilog library for ASIC and FPGA designers

opentitan

OpenTitan: Open source silicon root of trust

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

riscy-soc

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

work_dir

INS_FPGA

wujian100_open

IC design and development should be faster，simpler and more reliable

xilinxboardstore