sync/atomic: "synchronizes-before" ordering is broken on Load/Store. about go

[seankhliao]

r1 == 0 && r2 == 1

isn't this simply: W1, (the two store ops), W2

[haruyama480]

sync/atomic uses AArch64's STLR* instructions.

go/src/internal/runtime/atomic/atomic_arm64.s

Lines 105 to 121 in ac17440

	TEXT ·Store(SB), NOSPLIT, $0-12
	MOVD ptr+0(FP), R0
	MOVW val+8(FP), R1
	STLRW R1, (R0)
	RET
	TEXT ·Store8(SB), NOSPLIT, $0-9
	MOVD ptr+0(FP), R0
	MOVB val+8(FP), R1
	STLRB R1, (R0)
	RET
	TEXT ·Store64(SB), NOSPLIT, $0-16
	MOVD ptr+0(FP), R0
	MOVD val+8(FP), R1
	STLR R1, (R0)
	RET

But, arm's hardware memory model allows memory accesses to different addresses to be "Re-order"ed.
https://developer.arm.com/documentation/102376/0100/Normal-memory

[haruyama480]

W1, (the two store ops), W2

Sorry, I don't understand. Could you give me some details?

[haruyama480]

(I added "R1" and "R2" for convention)

[haruyama480]

Sorry, I get it.

You meant R1, W1, W2, R2.

[haruyama480]

I fixed my code, and confirmed the test works.

-                       r1 := atomic.LoadInt32(&x)
-                       r2 := atomic.LoadInt32(&y)
-                       if r1 == 0 && r2 == 1 {
+                       r1 := atomic.LoadInt32(&y)
+                       r2 := atomic.LoadInt32(&x)
+                       if r1 == 1 && r2 == 0 {

Thank you for comments!

(Though I'm curious there are correct ordering with arm's STLR/LDAR instructions, I will study it. )

[haruyama480]

In my macOS, TSO mode is enabled. So, If I turn it off or use another arm, fixed test may fail possibly.

% sysctl net.inet.tcp.tso
net.inet.tcp.tso: 1