Comments (4)
dsidler
commented on June 22, 2024
1
The project was only tested with vivado 2019.1
from fpga-network-stack.
Oxygen-Chu
commented on June 22, 2024
The project was only tested with Vivado 2019.1
OK, I will test it later on Vivado 2019.1.
Thank you :- )
from fpga-network-stack.
Oxygen-Chu
commented on June 22, 2024
The project was only tested with vivado 2019.1
I have successfully compiled the project with
RHEL 8.1 + Vitis 2019.2
The key is update the Linux kernel to the latest version.
Thank you, Dsidler :- )
from fpga-network-stack.
Oxygen-Chu
commented on June 22, 2024
I have successfully compiled the project with
RHEL 8.1 + Vitis 2019.2
from fpga-network-stack.
Related Issues (20)
- Request for a up-to-date example design HOT 1
- TCP windows size exeded then stall HOT 1
- can you also please provide the test vectors for the RoCE module? Thank you !! HOT 1
- It's invalid to open dcp file in dir ip using vivado 2019.1
- Do you have source file for SmartCamctl ?
- how
- Linux TCP stack not reacting to SYN packet sent from the FPGA board HOT 1
- synthesis error : "tcp_ip_top.v" instantiates a mismathed version of "network_stack.v"?
- Can it work with Vcu 707
- How to access RoCE QP states
- How to generate bitstream (wiki is outdated) HOT 19
- There may be a bug in the txEngMemAccessBreakdown() module? HOT 1
- How to change the IP address?
- RoCEv2 ICRC issue
- Can this design be targeted on Alveo u50 xilinx_u50_gen3x16_xdma_5_202210_1 platform?
- How to Install the HLS IP core to the IP repository
- Build error - ERROR: [HLS 207-3776] use of undeclared identifier 'FNS_ROCE_STACK_MAX_QPS'
- Trying out TCP/IP stack
- How to use RoCEv2?
- The board replied with an incorrect packet when establishing the TCP connection
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