Comments (8)
The fastest workaround that I see is that you manually modify
blis/config/rv64i/make_defs.mk
Line 49 in 6b894c3
and revise the ABI to -mabi=lp64d
.
You raise a good point here. There is not ABI detection. The RISC-V targets choose what we assumed is the most common one. For a generic rv64i target, we assumed this to be lp64
.
@leekillough Do you have more thoughts on this?
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I will add ABI auto-detection, just like architecture auto-detection which already exists ( frame/base/bli_riscv_detect_arch.h ), but the stubs symptom is more of a toolchain issue. In my toolchain build script, I have:
build_riscv_toolchain() (
cd -- "$RISCV/$RISCV_TOOLCHAIN"
make -j16 linux
if [[ $RISCV_COMPILER = llvm ]]; then
if [[ $RISCV_SIZE = 64 ]]; then
ln -sf stubs-lp64d.h "$RISCV/sysroot/usr/include/gnu/stubs-lp64.h"
ln -sf stubs-lp64d.h "$RISCV/sysroot/usr/include/gnu/stubs-lp64f.h"
else
ln -sf stubs-ilp32d.h "$RISCV/sysroot/usr/include/gnu/stubs-ilp32.h"
ln -sf stubs-ilp32d.h "$RISCV/sysroot/usr/include/gnu/stubs-ilp32f.h"
fi
fi
)
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The workaround of changing line 49 to -mabi=lp64d does work for me and the checks all pass but it does not use the CPU's full feature set of rv64imafdc_zicsr_zba_zbb as I think your code its restricted to rv64i so it may run slower thank it could.
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The code currently detects rv64imafdc
and is not restricted to rv64i
, but I will add zba
, zbb
, zbc
, zbs
, and zfh
, since those are detectable at compile-time. Zicsr
and Zifencei
are not currently detectable at compile-time with the latest C API, but Q
->D
->F
implies Zicsr
.
Clang does not enable the __riscv_v
or __riscv_vector
macros or choose -march=...v
by default, even if it's built with vectors enabled, so we use a workaround to force vectors with -march=...v
in the rv32iv
and rv64iv
configurations.
You can test the autodetection method this way:
$CC -E frame/base/bli_riscv_detect_arch.h | grep '^[^\#]'
-DFORCE_RISCV_VECTOR
is specified for rv32iv
and rv64iv
because Clang does not enable vectors by default even if it's capable of them.
I will submit a PR shortly.
from blis.
Thank you. Do you plan to create a release in the near future with the RISC V code included?
from blis.
Thank you. Do you plan to create a release in the near future with the RISC V code included?
I think BLIS is mostly released on a continuous integration model, so the latest master
has the RISC-V code already, modulo the ABI header stub issues you've run into, and as soon as a PR is merged, it will have the changes.
from blis.
That is correct but some distributions like GENTOO tend to wait for an official release before providing the updated package.
from blis.
@apcameron: In case it wasn't clear, rv32i
, rv32iv
, rv64i
and rv64iv
are base RISC-V configurations, since 32/64-bit and vector/non-vector, are the major categories which need to be separated. They are not the -march=
flags passed to the compiler. Whether a particular RISC-V target supports M
, A
, F
, D
, C
, etc., is not a part of the main BLIS configuration name, but gets automatically determined and used at build-time. It would be too hard to enumerate every possible combination of RISC-V extensions into the BLIS configuration name, so there are only 4 main ones.
The BLIS RISC-V implementation intentionally does not pass floating-point to assembly functions by value, so the "base" ABI of ilp32
or lp64
should be sufficient, which is why they were used in the makefiles. If you add the stubs to the toolchain with the symlink commands I listed above, then you should not get the missing stubs build error when BLIS uses -mabi=lp64
.
PR750 should make the missing headers error go away, and may negligibly improve performance by using ilp32d
or lp64d
when possible.
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