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a-convolution-kernel-implemented-by-vivado-hls

This project implements a convolution kernel based on vivado HLS on zcu104

awesome-zero-knowledge-proofs

A curated list of awesome things related to learning Zero-Knowledge Proofs (ZKP).

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

bringup-bench

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!

ces_util_lib

CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-test

Unit testing for cocotb

cocotbext-axi

AXI interface modules for Cocotb

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

deploying_cnn_on_fpga_using_opencl

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

fpga_snark_prover

An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs

goldilocks

goldilocks_benchmarks

gzipdecomp_alveo

Decompression of GZIP files for Xilinx Alveo

iverilog

Icarus Verilog

open-nic

AMD OpenNIC Project Overview

openspike

Fully opensource spiking neural network accelerator

proteus

pysvinst

Python library for parsing module definitions and instantiations from SystemVerilog files

readings-in-computer-architectures

Readings in Computer Architectures

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

verilog-axis

Verilog AXI stream components for FPGA implementation

winterfell

A STARK prover and verifier for arbitrary computations

zkevm-prover

zkEVM prover in C++