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2022_software_engineering

2022linuxexperiment

Experiment

btgfw

自建梯子教程-翻墙-科学上网-google

caption_contest_corpus

Corpus to accompany: "Do Androids Laugh at Electric Sheep? Humor "Understanding" Benchmarks from The New Yorker Caption Contest"

combinational-bnn

System Verilog code describing a fully combinational binarized neural network.

cssummercamp2023

ddr4sim

DDR4 Simulation Project in System Verilog

dm-zap

dm-zap device mapper

extfuse

Extension Framework for FUSE

fannyhhh.github.io

fuse-kernel-instrumentation

fuse-stackfs

geardb

GearDB: A GC-free Key-Value Store on HM-SMR Drives with Gear Compaction

how-to-make-a-computer-operating-system

How to Make a Computer Operating System in C++

leveldb

LevelDB is a fast key-value storage library written at Google that provides an ordered mapping from string keys to string values.

libfuse

The reference implementation of the Linux FUSE (Filesystem in Userspace) interface

ostep-projects

Projects for an undergraduate OS course

real-time-fxcm

高频量化对冲交易自动化

sdn-ddos-detection-and-mitigation-using-ml-and-statistical-methods

Mininet+DDos

sdn-network-ddos-detection-using-machine-learning

sdn network ddos detection using machine learning

sdn_ddos_simulation

An attempt to detect and prevent DDoS attacks using reinforcement learning. The simulation was done using Mininet.

se2022

20级软件工程

smr_fs-ext4

solutions-to-hdlbits-verilog-sets

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

springboot

systemverilog-uart

Simple UART transmitter and receiver

systemverilogreference

training labs and examples

systermverilog-systemverilogassertions

Examples and reference for System Verilog Assertions

tpcc-mysql

verification-of-fifo-using-systemverilog

Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog. Created components like generator, driver, monitor, scoreboard, interface, environment, and testbench.