Synthesis times about financialmodels_amazonf1

[lavagno]

Synthesis time is negligible (a few minutes). Placement and routing took about 5 hours on a fairly recent 8-core machine with plenty of RAM. Best regards, Luciano Lavagno

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On Mon, 23 Apr 2018 18:51:22 +0000 (UTC) Mahdi Jelodari ***@***.***> wrote: Do you mind including the `synthesis times` in the performance table? https://github.com/KitAway/FinancialModels_AmazonF1#performance-on-amazon-f1-fpga -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: #2

-- EU Cell [phone] US Cell [phone] Office [phone] http://www.det.polito.it/personale/scheda/%28nominativo%29/luciano.lavagno Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy

[Mahdi89]

Thanks for your reply,

Agree that the implementation and RTL generation phases take no more than few minutes but do you take HLS process into account as well? for me Architecture Synthesis (see below) took almost 4.5 hrs with the following params:
const int blackScholes::NUM_RNGS=64; const int blackScholes::NUM_SIMS=512; const int blackScholes::NUM_SIMGROUPS=1024; const int blackScholes::NUM_STEPS=256;
logs:
... INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 02:29:13 ; elapsed = 04:19:57 . Memory (MB): peak = 10211.941 ; gain = 9865.387 ; free physical = 347 ; free virtual = 4327 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'blackAsian' ... WARNING: [SYN 201-103] Legalizing function name 'exp_generic<float>' to 'exp_generic_float_s'. WARNING: [SYN 201-103] Legalizing function name 'sin_or_cos<float>' to 'sin_or_cos_float_s'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'init_array' INFO: [HLS 200-10] ----------------------------------------------------------------

[lavagno]

You are right.... With the parameters in the repository, considering for example Black Scholes European option, Vivado HLS takes longer than what is typical. I see 2 hours and 40 minutes for Vivado HLS and 6 hours for Vivado. Best regards, Luciano Lavagno

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On Tue, 24 Apr 2018 12:13:59 +0000 (UTC) Mahdi Jelodari ***@***.***> wrote: Thanks for your reply, Agree that the implementation and RTL generation phases take no more than few minutes but do you take HLS process into account as well? for me Architecture Synthesis (see below) took almost 4.5 hrs with the following params: `const int blackScholes::NUM_RNGS=64; const int blackScholes::NUM_SIMS=8; const int blackScholes::NUM_SIMGROUPS=16; const int blackScholes::NUM_STEPS=256; ` logs: `... INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 02:29:13 ; elapsed = 04:19:57 . Memory (MB): peak = 10211.941 ; gain = 9865.387 ; free physical = 347 ; free virtual = 4327 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'blackAsian' ... WARNING: [SYN 201-103] Legalizing function name 'exp_generic<float>' to 'exp_generic_float_s'. WARNING: [SYN 201-103] Legalizing function name 'sin_or_cos<float>' to 'sin_or_cos_float_s'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'init_array' INFO: [HLS 200-10] ---------------------------------------------------------------- ` -- You are receiving this because you commented. Reply to this email directly or view it on GitHub: #2 (comment)

-- EU Cell [phone] US Cell [phone] Office [phone] http://www.det.polito.it/personale/scheda/%28nominativo%29/luciano.lavagno Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy

[Mahdi89]

Thanks for your reply Luciano,

I see, that makes sense, Thanks
.