pgen.v - main Verilog HDL file with pgen module
pgen.vt - test bench for pgen.v module (look pgen_present)
pgen_top.v - the top module for quartus project (look pgen_present)
pgen_present.pdf - PSU IceCube group meeting presentation about pgen
(contains code (s.2,3), top level module scheme (s.4), test bench with vsim output (s.5), FPGA/oscilloscope test output(s.6))