xfer2 glitch on cs. about py-spidev

[ead0601]

I wanted to add that the glitch occurs near the begining of the transfer, and for the rest of the burst of 4 bytes, the glitch is not there.

[ead0601]

I added the following to /boot/config.txt

core_freq=250

This disables the auto frequency throttling, and fixes the core frequency.

1. I no longer see the glitch.
2. However, very intermittently, I receive the incorrect data. I have slowed down the transfer and ensured proper grounds, and a problem still occurs. The SI looks good on a scope.

Given the improved performance with the "core_freq" setting, I can implement a retry work around. Luckily the first couple of MISO bits are fixed, so I will know when to retry.

Something, is still not Kosher.

Edward

[doceme]

It sounds like this is a Pi 3 problem or kernel driver issue and not related to spidev.

[ead0601]

The problem was fixed with the lastest pull request by billmccartney :

#53 (review)