Related Issues (16)
- Some boards use two-line per port xdc format HOT 1
- Mismatch in UART pins between vivado board file and .xdc file for CMOD-A735 HOT 1
- Is there a reason why the Nexys A7 boards have LVCMOS18 on SW[8] and SW[9] while the other ports are LVCMOS33? HOT 1
- Voltage constraints HOT 1
- Cora Z7 > Pmod JB > reversed pin assignment? HOT 1
- The constraint file of genesys2 is inconsistent with the document HOT 1
- RX/TX IN/OUT in interface names mixed
- Add CONFIG_VOLTAGE and CFGBVS configuration options for (Nexys) boards
- Files have no copyright
- Arty z7-10 missing pins?
- Typo in Cmod-S7-25-Master.xdc HOT 1
- Typo in cora z10 xdc HOT 1
- Wrong Pin assignment HOT 1
- Arty-A7 35 and 100
- DDR pin HOT 3
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from digilent-xdc.