how to import the ip to vivado? about yolov2_xilinx_fpga

[dhm2013724]

It depends on your chip that you selected. The tcl and xdc files are not important, and they are just used for constructing Linux operating system. Just follow the block design, enable several HP ports to connect the ip with PS.

[overing1314]

but I didn't get any ip call "Yolo2_FPGA"
can you share the ip file to me? or teach me how to import the ip Yolo2_FPGA.
I can not finish the block design wihout the Yolo2_FPGA ip.

[dhm2013724]

The name may be changed, related codes are included in HLS dir. This doesn't matter.

[SoumyaDeshapnde]

To create the ip for Yolov2..
do I have to select option 1: package current project?
or create an AXI4 peripheral and then add sources to it?

[dhm2013724]

To create the ip for Yolov2..
do I have to select option 1: package current project?
or create an AXI4 peripheral and then add sources to it?

The YOLOv2 IP is designed by Vivado HLS, and there's a button to export the design to ip format. You only need to import the ip that HLS exported in related Vivado project.

[SoumyaDeshapnde]

To create the ip for Yolov2..
do I have to select option 1: package current project?
or create an AXI4 peripheral and then add sources to it?

The YOLOv2 IP is designed by Vivado HLS, and there's a button to export the design to ip format. You only need to import the ip that HLS exported in related Vivado project.

okayy..
So, just to clarify, I should do a software simulation ie step 2 (HLS Accelerator and Simulation) along with the weights generated from step 1 and then find the button that exports the design to ip format, is this right?