Hello, your work is very good, but I have some questions, can you give some advice? about yolov2_xilinx_fpga

[dhm2013724]

Hello, I am recreating your code in vivado_hls2017. It takes 45 minutes to test a picture. What is the reason? I want to reproduce your code on the ZCU102. Can you give some advice?

C Simulation always takes too much time, and I have warned others when I uploaded the testbench. There is no problem. I don't suggest you evaluate this design in ZCU102, because it is not designed to so high-level FPGA chip, and many architectures and considerations are not suitable. Maybe you can try https://github.com/Xilinx/CHaiDNN. which is designed for MPSOC

[wu-y]

Hello, I found that you are using the normal transfer mode when transferring data. If you use DMA transfer, the speed is faster; you now have 2*32 parallelism due to the board, if you don't consider resource issues. To improve parallelism, where do I need to make changes?

[dhm2013724]

Hello, I found that you are using the normal transfer mode when transferring data. If you use DMA transfer, the speed is faster; you now have 2*32 parallelism due to the board, if you don't consider resource issues. To improve parallelism, where do I need to make changes?

I have implemented the 4*32 parallelism in Zedboard. If you want to increase the parallelism, generally there are two ways to achieve it. First, try to decrease the data precision, and you will have more resoures to design more mul-add unit. Second, You can partially or completely unroll the 2-3 dimension of six-dimensional convolution to design computing arrays with higher utilization or higher parallelism. I have just partially unrolled 2 dimension. In addition, you can try other optimizations as well, like Winograd.