deilt Goto Github PK

accelerated-http-proxy

:arrow_double_down: 采用多线程的浏览器加速代理，将校园网带宽利用到100%

amba_axi_ahb_apb

AMBA bus lecture material

awesome-dv

Awesome ASIC design verification

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

basic_verilog

Must-have verilog systemverilog modules

c-crashcourse

C语言教程+博客+代码演示+课程设计。 帮助初学者更好的理解 C 难点，提升代码量！ For beginners:C tuition/self-learning

chatgpt_academic

科研工作专用ChatGPT拓展，特别优化学术Paper润色体验，支持自定义快捷按钮，支持markdown表格显示，Tex公式双显示，代码显示功能完善，新增本地Python工程剖析功能/自我剖析功能

code-source

code_training

cplusplusthings

C++那些事

cpp-primer-plus-6th

《C++ Primer Plus 第6版（中文版）》原书代码、习题答案和个人笔记，仅供学习和交流。

cpp_primer_answers

《C++ Primer》第五版中文版习题答案

cpp_primer_practice

搞定C++:punch:。C++ Primer 中文版第5版学习仓库，包括笔记和课后练习答案。

deilt.github.io

deilt_riscv

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

fpga

数字IC相关资料

gdindex

A Google Drive Index built with Vue Running on CloudFlare Workers

github520

:kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）

goindex-theme-acrou

This is a goindex template

hdl-bits-solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

hw

RTL, Cmodel, and testbench for NVDLA

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

ics-pa-gitbook

jasminum

A Zotero add-on to retrive CNKI meta data. 一个简单的Zotero 插件，用于识别中文元数据

machine-learning-homework

Matlab Coding homework for Machine Learning

missing-semester-cn.github.io

the CS missing semester Chinese version

mlofandrew-ng

吴恩达机器学习课程的讲义，欢迎大家一起学习

mpsoc-dv

Multi-Processor System on Chip verified with UVM/OSVVM/FV

oh_ip

Verilog library for ASIC and FPGA designers