Comments (7)
Crossbar networks: "Typically there is trade off between the size of hardware resources (gates, flip flops, wires) and measures of congestion, such as bisection bandwidth"
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FIR Filter with Vivado synthesis analysis
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Educational RISC-V implementation: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md
CC @gabizon103
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The Genesis 2 project from Stanford has a bunch of publications on generators they built: https://github.com/StanfordVLSI/Genesis2/wiki/Publications
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vlsiffra
parameterized adders and multipliers implemented using Amaranth HDL
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Vitis BLAS library: https://xilinx.github.io/Vitis_Libraries/blas/2022.1/index.html
Probably provides a reasonable baseline for an FPGA based BLAS implementation
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Related Issues (20)
- Current website formatting doesn't meet WCAG text accessibility guidelines HOT 1
- Build docker container for all ADL tools HOT 2
- Generic bundle transformers
- Cleanup deadline code
- Shortform syntax for external parameter access HOT 1
- Unused variable warning
- BLAS evaluation HOT 1
- Partial Streaming FFTs HOT 3
- ASIC Flows for Evaluation HOT 2
- Instance borrow syntax should support references to instance's existential parameters HOT 4
- Bundle assignments of same length HOT 1
- Add a way to specify global values used in the gen framework
- No longer testing against rust panic messages
- Removing reliance on calyx dockerfile
- If-expressions for parameters HOT 1
- Providing parameters to `main` component on compilation. HOT 3
- Externally-provided parameters HOT 4
- Extend assert syntax HOT 1
- Better error message for `attempt to subtract with overflow` HOT 1
- Higher order Filament HOT 3
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