crsullivan13 Goto Github PK

368connect4

448-battleship

581-team25

arm-trusted-firmware

Raspbery Pi fork for Pi5

bankdefenseboards

Real world board test repo for bank defense project

bru-workload

bwreg

Code relating to BRU and "bank-aware" BRU

cachebankdos

cfg-dataflow

Simple CFG creation and data flow analysis on a VERY small subset of llvm

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-book

Digital Design with Chisel

chisel-examples

Chisel examples and code snippets

crsullivan13.github.io

dosvbru-firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

firemarshal

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

graphing-bankdefense

Graphing scripts for bank defense project (messy)

isolbench

A set of synthetic benchmarks used in IEEE RTAS 2016 paper by Prathap et al.,

linux-fsim

Linux kernel source tree

palloc

DRAM Bank-Aware Kernel Memory Allocator

pi5-way-part

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-hpmcounters

A simple utility for doing RISC-V HPM perf monitoring.

rocket-chip

Rocket Chip Generator

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

slice-reverse

Code from the paper "Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters", with updates for Kaby Lake CPUs

visr

KWS voice activated slideshow remote

zenhammer

A Rowhammer fuzzer for AMD Zen-based systems (USENIX Security '24).