Comments (1)
From reading the source code, it looks like Ramulator assumes the presence of something like a write-data cache in the memory controller (MC) capable of buffering the write data corresponding to all the write requests in the write queue (which is not unreasonable, since the write data of a 32 entry write queue can be buffered with a SRAM storage of 32x64B = 2KB/channel in the MC). So, whenever there are requests as you described above (i.e. a write followed by reads to the same address before the completion of the write request), all these read requests are treated as hits in the write-data cache in MC and returned as complete in the next clock cycle. Since, these requests do not access the DRAM, the data transfer speed and other DRAM timing parameters do not come into the picture.
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Related Issues (20)
- Self Refresh and Refresh Wrong Prerequisites
- core dumped HOT 4
- Why is update_serving_requests for WRITE requests called at the time when they are issued to the DRAM?
- gem5 version 10231 now is unavailable HOT 4
- Does it take care of Cache simulation on the memory trace?
- ramulator
- DRAM trace mode: No mechanism to identify the arrival time of the requests HOT 1
- GDDR5 channel_width should be 32, not 64
- stream read & write requests are handled every 4 cycles? HOT 2
- Heterogeneous Memory can be used in Ramulator?
- Problem with Ramulator. HOT 2
- Problem with Ramulator
- No rule to make target 'obj/.depend'
- Possible wrong address mapping HOT 2
- Error while using Trace Generator tool in Ramulator HOT 2
- Execution getting killed when running using Zsim trace file with 2 billion instructions.
- the cycle for DDR4 need to be updated
- multi-core simulation has a problem in handling writebacks for cache filtered mode
- memory tick function of DDR3 configuration
- deploy rowhammer in the ramulator
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