completion time and queue hit about ramulator

[dhiraj113]

From reading the source code, it looks like Ramulator assumes the presence of something like a write-data cache in the memory controller (MC) capable of buffering the write data corresponding to all the write requests in the write queue (which is not unreasonable, since the write data of a 32 entry write queue can be buffered with a SRAM storage of 32x64B = 2KB/channel in the MC). So, whenever there are requests as you described above (i.e. a write followed by reads to the same address before the completion of the write request), all these read requests are treated as hits in the write-data cache in MC and returned as complete in the next clock cycle. Since, these requests do not access the DRAM, the data transfer speed and other DRAM timing parameters do not come into the picture.