Comments (2)
Another issue: DMINFO.version should be 1, not 0.
from rocket-chip.
This and other issues have been resolved in uncore.
from rocket-chip.
Related Issues (20)
- Mill resolve error HOT 1
- Verilog generation HOT 1
- [Proposal] Nextgen rocket-chip planning thread. HOT 9
- Error when building the project HOT 3
- Rocket updates sepc and stval in M mode HOT 2
- Discrepency between simulation with and without traces HOT 2
- HART specific opearations at DRAM controller / adding hartid to memory requests
- MCAUSE register holds wrong exception HOT 1
- RoCC: io.mem.req.ready stuck
- Debugging section of README.md leads nowhere
- Add support for desiredName overrides for ClockDomains HOT 1
- the usage of cover and cover point, and how to coordinate with backend. HOT 1
- Error: Assertion failed: 'A' channel re-used a source ID when running simulation in QuestaSim HOT 1
- class RocketChip$macro$3 needs to be abstract. HOT 3
- Bus Error Unit cannot find implicit clock when RocketTile crossingType is set to RationalCrossing HOT 2
- vcs compile error
- Replay queue depth insufficient for RoCC accelerators
- unable to build the C emulator due to missing verilog.h file
- Make verilog Error HOT 4
- Java compilation error, prompting no byte 4096 alignment HOT 3
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