How do I control/redefine illegals about riscv-dv

[taoliug]

I'd recommend you extend below class and add constraint to avoid using opcode of B instructions.
https://github.com/google/riscv-dv/blob/master/src/riscv_illegal_instr.sv

[agrobman]

I just added
instr_bin[11:7] != 2; // do not generate target SP
to
instr_bit_assignment_c constraint

[taoliug]

I think it's better to make sure it's actually generating an illegal instruction. Otherwise, it could generate a valid instruction without proper constraint, which may do something crazy and break the program execution. For example, you could potentially generate load/store instruction without proper address, or branch/jump instruction which could lead to a dead loop.

For the sp constraint, depending on the instruction format, you might need to constraint different bit position, which may make this solution more complicated to implement.

[agrobman]

I think target register is always in the same position in the instruction … From: taoliug <[email protected]> Sent: Tuesday, September 17, 2019 3:37 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] How do I control/redefine illegals (#164) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. I think it's better to make sure it's actually generating an illegal instruction. Otherwise, it could generate a valid instruction without proper constraint, which may do something crazy and break the program execution. For example, you could potentially generate load/store instruction without proper address, or branch/jump instruction which could lead to a dead loop. For the sp constraint, depending on the instruction format, you might need to constraint different bit position, which may make this solution more complicated to implement. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#164>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G547RW2S67ZXSUDECGGLQKE5XDANCNFSM4IXS7BWA>.

[taoliug]

It's not always true for the compressed instructions. Besides, bit [11:7] could be use for other purposes if there's no rd for the instruction. This constraint ends up constrains something else which could pose a hole in the randomization.

[agrobman]

You are correct – but since we got B – there is even bigger hole. I’m looking for better, systematic way to generate illegals, than manually written constraints … The RTL instruction decoder is written as pretty simple PLA table , much more clear/reviewable , than these constraints - would be nice to have something like this to generate illegals: .definition clz = [011000000000.....001.....0010011] ctz = [011000000001.....001.....0010011] pcnt = [011000000010.....001.....0010011] slo = [0010000..........001.....0110011] … .decode rv32i[clz] = { alu zbb rs1 rd clz } rv32i[ctz] = { alu zbb rs1 rd ctz } rv32i[pcnt] = { alu zbb rs1 rd pcnt } rv32i[slo] = { alu zbb rs1 rs2 rd slo } …. So illegal is something that is not defined in .definition .decode defines flags/decoder outputs which used in the CPU pipe and execution units Using in .decode a class type like B, I, M, F .. etc, additional constraints for illegal would be for ex “F” if floating is not implemented … From: taoliug <[email protected]> Sent: Tuesday, September 17, 2019 4:16 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] How do I control/redefine illegals (#164) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. It's not always true for the compressed instructions. Besides, bit [11:7] could be use for other purposes if there's no rd for the instruction. This constraint ends up constrains something else which could pose a hole in the randomization. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#164>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G543BWKLWAVRRLWVISWDQKFCK3ANCNFSM4IXS7BWA>.

[taoliug]

I think these are just two different ways to implement it. Either have a full legal binary encoding table and generate something not belongs to this table, or directly constraint the binary to target the illegal encoding. I will consider to refactor this class a bit to make it more readable.
I am closing this issue for now as I believe the original issue is solved. Thanks for reporting.