Comments (1)
I reopened issue #14, let's discuss this issue there.
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Related Issues (20)
- Can not find file `VECTOR_INCLUDE("riscv_instr_cover_group_inc_cg_sample.sv") etc file path HOT 1
- WRITE_GPR in gen_signature_handshake() produces invalid assembly
- use pyflow error: ModuleNotFoundError: No module named 'ucis.ucdb' HOT 1
- riscv_csr_test fails at generation
- RVC Instruction gpr coverage collection omissions for CR/CI/CSS formate
- no_load_store switching option
- Test generation failed for riscv_amo_test
- how to generate compressed instructions regression test HOT 3
- pyflow callstack_gen randomize fail HOT 1
- [pygen] riscv_rand_instr_test run failed
- mmode_exception_handler is not considering the instruction misaligned, load address misaligned, store/amo address misaligned
- for debug mode, how to modify link.ld to match debug rom enter addr HOT 1
- for debug mode, how to modify link.ld to match debug rom enter addr
- for debug mode, how to modify link.ld to match debug rom enter addr
- for debug mode, how to modify link.ld to match debug rom enter addr
- Instruction Address Misalign Exception
- use ovpsim .Why is there no verbose log instruction HOT 5
- spike
- The spike simulation gets stuck in an endless loop HOT 2
- rv64gc failing spike due to exception trap_store_address_misaligned HOT 2
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